A hierarchical technique for minimum-width layout of two-dimensional CMOS cells

We present a hierarchical technique, based on integer linear programming (ILP), to generate area-efficient layouts of relatively large complex CMOS cells in the two-dimensional (2-D or multi-row) style. First, the CMOS circuit is partitioned into subcircuits called clusters. Next, the set of all minimum-width 1-D placements (chain covers) are generated for each cluster and form the input to the ILP model. The model aims at selecting exactly one cover for each cluster such that the overall 2-D cell width is minimized. In the process, all possible diffusion sharing between transistor chains belonging to clusters are considered; the inter-row connections that contribute to the overall cell width are also reduced. Experimental results demonstrate that the technique reduces run times by several orders of magnitude over non-hierarchical methods, and yields optimal or near-optimal layouts in most cases.