A Low Noise CMOS Phase Locked Loop

A 5V, 0.6μm CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in CMSC 0.6μm 5V 2P2M CMOS technology, the simulation results show that the PLL operates within the frequency range between 100MHz to 500MHz, and the phase noise are -89dBc/Hz and -100dBc/Hz at 100KHz and 1MHz offset frequency.