SEE Characterization of the New RTAX-DSP (RTAX-D) Antifuse-Based FPGA

A comprehensive SEE characterization at high-frequencies (up to 120 MHz) of the new space-flight RTAX-D antifuse-based FPGA family is presented. SEE hardening-by-design techniques in the main FPGA programmable architectures have been implemented. It is evaluated in-beam to show their efficacy in mitigating SETs with little area and time penalty. In particular, SEU/SET mitigation solutions were implemented in the new embedded DSP blocks and the FPGA core and tested in heavy-ion beams. Comparing to its predecessor, RTAX-S, these mitigations reduce the overall orbital error-rates by an order of magnitude.