An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process

An advanced 0.5- mu m CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N/sup -/ and boron P/sup -/ regions for improved short-channel behavior.<
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