Multi-Gbit I/O and interconnect co-design for power efficient links

The co-design of a 10Gb/s 45nm CMOS transceiver and low-loss interconnect for parallel links demonstrates 1.4-2.4pJ/bit I/O power efficiency. A C4 bump pattern with an effective 20:3 signal to ground ratio is implemented with on-die transmission line routing to escape from the I/O circuitry to the package-die interface. Top-of-the-package connector based (TPCB) interconnects, including high density interconnect (HDI), bonded polyimide (PI) flex, liquid crystal polymer (LCP) flex and micro-twinax cables, are trace length matched in bundles of 9 or 10 I/O lanes to minimize clocking power while requiring only 2-tap TX equalization and 106-373mVpp-diff TX swing. The link measured maximum lane-to-lane phase mismatch ranged from 6ps to 22ps.