Integration of $\hbox{LaLuO}_{3} \ (\kappa \sim \hbox{30})$ as High-$\kappa$ Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process

The integration of lanthanum lutetium oxide (LaLuO
₃
) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO
₃
/Si interface showed a very thin silicate/SiO
₂
interlayer with a D
_it
level of 4.5 × 10
¹¹
(eV · cm
²
)
^-1
. Fully depleted n/p-MOSFETs with LaLuO
₃
/TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high I
_on
/I
_off
ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO
₃
on SOI are similar to the mobilities in reported Hf-based high-κ devices.