Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization

The advent of multiple-input–multiple-output (MIMO) techniques has resulted in the generation of new design problems, especially in the baseband processing task of symbol detection. Lattice reduction (LR)-aided detection techniques have emerged as a low-complexity method to achieve the same diversity as the maximum likelihood detector. In this article we explore efficient hardware realization of the complex Lenstra, Lenstra, Lovász (CLLL) LR algorithm. We accomplish this task by first developing an understanding of the complex relationship between algorithm and hardware considerations. After proposing hardware-motivated algorithm modifications, we apply this understanding to the design of a 4
$\,\times\,$
4 CLLL processor for MIMO detection. Hardware realization results on a Xilinx XC4VLX80-12 FPGA demonstrate that the CLLL processor has a throughput of over 3.5 M channel matrices per second, outperforming previously disclosed hardware realizations. In addition, the algorithm modifications and design procedures that we propose are easily applied to larger MIMO system sizes.