A Configurable FPGA Implementation of PEG-based PS-LDPC Decoder

Low-density parity-check (LDPC) codes form an important subclass of error correcting coding techniques, and its implementation has been hot spot of domains such as signal process, magnetic recording or next generation communication for years. This paper proposes a configurable FPGA implementation of Partition-and-Shift LDPC decoder based on Min-Sum algorithm. An MPEG algorithm is introduced to reduce the complexity of searching for closed paths in shift matrix. And a routing paths switch concept is proposed to realize the expected configurability. Benefits of the proposed technique are demonstrated with FPGA design for differently configured PS-LDPC decoders which all achieve a Gbps throughput, low hardware cost and excellent BER performance at 16 iterations.