A VLSI chip for image compression using variable block size segmentation

The paper describes a VLSI architecture for lossless image compression based on the Variable Block Size Segmentation (VBSS) scheme. The VBSS scheme segments the image into variable size blocks, extracts the redundancy features in them, and encodes the blocks using suitable coding techniques in order to obtain maximum compression. The scheme is computationally intensive and time consuming when implemented in software. The proposed architecture fully utilizes the principles of parallelism and pipelining in order to obtain high speed and throughput. It requires simple basic cells and regular nearest-neighbor communication making it suitable for VLSI implementation. A prototype CMOS VLSI chip implementing the image characteristics extraction subsystem has been designed and verified using the Cadence design tools at the University of South Florida. The chip can be used to process an image of 1024/spl times/ 1024 pixels in 1.3 ms operating at a frequency of 100 MHz.