P+P: parallel pattern and parallel fault simulator for synchronous sequential circuit

This paper describes P+P, a fast fault simulator for synchronous sequential circuits. P+P uses parallel patterns in good machine simulation (GMS) and parallel faults in faulty machine simulation (FMS). In addition, P+P features several new techniques, such as global circuit levelization, cone operation, global fault grouping, levelized events and improved ID etc., in order to increase performance. The algorithm is realized on SUN SPARC-2 with random patterns. P+P runs on most of the ISCAS benchmark circuits. These experiments show that P+P is much faster than primary P+P algorithm.