A 500 MS/s 10-bit CMOS D/A converter

This paper presents a low-power high-speed 10-bit D/A converter. The chip is implemented in a 0.45-/spl mu/m ASIC CMOS technology and active chip area is 0.8 mm by 0.4 mm. Its dc DNL (differential nonlinearity) is within 0.53 LSB. The chip dissipates 60 mW at 500 MS/s with 57 dB spur-free dynamic range. The normalized power consumption is only 120 /spl mu/W/MHz, while achieving the highest sampling rate ever reported for a 10-bit D/A in a CMOS technology.