A novel VLSI design for survivor memory unit in Viterbi decoder

Since Viterbi Decoder (VD) plays an important role in the realization of HDTV and other digital systems, many efforts have been made on the research and development of the integration of VDs. Survivor Memory Unit (SMU) is one of the three major units which consist of a Viterbi decoder. A novel VLSI approach for realizing SMU differing from the traditional technique is proposed in this paper. A rate=4/5, v=3, L=15, 32 QAM Viterbi decoder with this new structure has been designed and passed the computer simulation.