Verification-oriented MBDD design for digital circuits

Efficient manipulation of Boolean functions is an important component of many CAD tasks. In this paper, a new and practical State Transition Graph (STG) construction method, which is based on the appending operation from standard gate MBDD (Max/Min Standard BDD Construction) is proposed. Obviously, a reduced STG in which the inputs and states are collapsed, is obtained. Finally, several experiment results are shown the effectiveness of the method.