FPGA-based 112Gb/s coherent DP-QPSK receiver and multi-stage PMD-PDL emulator for fast evaluation of digital signal processing algorithms

We developed an FPGA based 112Gb/s coherent DP-QPSK receiver and a multi-stage PMD-PDL emulator that resembles real fibre conditions. Long-term, low penalty signal reception under severe PMD (31.2ps mean) and PDL (1.3dB mean) is experimentally demonstrated.