ANSYS-based 3D-SoC thermal electric coupling model

In order to thermal-design 3D-SoC, one novel thermal electric coupling ANSYS model is built with features on (1) unit type of SOLID69, (2) 6-die stack-layers, (3) innerdie Cu-line 1 ∼ 3 as interconnect-complex level, (4) die current density converted into voltage across Cu-line, and (5) ITRS-2007 data, for scanning out top-layer temperature decrease factors. Four key room temperature tendency decrease factors were grasped: (a) tc (copper interconnect thick), (b) tp (package thick), (c) tsi1 (die1 thick), and (d) kp (package thermal conductivity).