Test-to-Failure of crystalline silicon modules

Accelerated lifetime testing of five crystalline silicon module designs was carried out according to the Terrestrial Photovoltaic Module Accelerated Test-to-Failure Protocol. This protocol compares the reliability of various module constructions on a quantitative basis. The modules under test are subdivided into three accelerated lifetime testing paths: 85°C/85% relative humidity with system bias, thermal cycling between -40°C and 85°C, and a path that alternates between damp heat and thermal cycling. The most severe stressor is damp heat with system bias applied to simulate the voltages that modules experience when connected in an array. Positive 600 V applied to the active layer with respect to the grounded module frame accelerates corrosion of the silver grid fingers and degrades the silicon nitride antireflective coating on the cells. Dark I-V curve fitting indicates increased series resistance and saturation current around the maximum power point; however, an improvement in junction recombination characteristics is obtained. Severe shunt paths and cell-metallization interface failures are seen developing in the silicon cells as determined by electroluminescence, thermal imaging, and I-V curves in the case of negative 600 V bias applied to the active layer. Ability to withstand electrolytic corrosion, moisture ingress, and ion drift under system voltage bias are differentiated according to module design. The results are discussed in light of relevance to field failures.