The CCD neural processor: a neural network integrated circuit with 65536 programmable analog synapses

The design, fabrication, and preliminary testing of an integrated circuit implementing neural network (NN) models with 256 on-chip, fully interconnected neurons and programmable analog synapses are reported. The integrated circuit was built using a charge-coupled-device-(CCD)-based architecture. A study of the current efforts to develop NN hardware reveals that the conventional electronic approach suffers from two major problems: (1) a tradeoff between the complexity of the synapse and the number of synapses per chip; and (b) the I/O (input/output) problem, namely, the slow communication between the chip and the surrounding environment. This approach circumvents the problems by using CCD arrays and/or a spatial light modulator as a short-term memory for the device. The preliminary results presented serve to validate the assumptions on which the CCD approach is based and to reassess the potential of this approach. The CCD architecture is based on two main assumptions: (a) the revolving charge packets in the CCD rings can complete several full cycles without substantial decay, (thus the required refresh of the matrix from an external memory will not significantly degrade the overall operation speed) and (b) the multiplication process, namely, the nondestructive sensing of the W/sub ij/ packets revolving in the CCD rings and their accumulation (provided the respective V/sub j/ is on) can be accomplished accurately and quickly. It is now clear that both these assumptions are valid.<
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