A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5
$\mu$
m
$\,\times$
37.8
$\mu$
m. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50
$~$
mA from a 1-V supply. The LDO has a quiescent current of 9.3
$\ \mu$
A, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).