Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuit

Addresses a proposed parallel hybrid dataflow architecture, a scalable dynamic load balancing circuit for the proposed architecture, and performance analysis, first, of the load balancing circuit and, second, the architecture using the load balancing circuit. The contributions and focus of this paper are: (1) that it first describes the requirements for and the framework of a parallel, medium to coarse grain, hybrid token controlled dataflow architecture. This paper only deals with real-time applications of the architecture. (2) The paper next describes the dynamic load balancing strategy for the hybrid dataflow architecture and a resulting mathematical model of the load balancing function required by the load balancing strategy. (3) The organization, design, and implementation of a basic digital circuit suitable for VLSI implementation which implements the mathematical model of the load balancing function required by the architecture is next presented. This circuit implements a control token mapping function and is therefore called a "token mapper". (4) It is next shown that the basic dynamic load balancing circuit (token mapper) design is scalable therefore allowing the hybrid dataflow architecture to be scalable. (5) The performance of the dynamic load balancing circuit is then analyzed at both the circuit and architectural systems level. A parallel simulation of the proposed parallel hybrid dataflow architecture employing its presented dynamic load balancing circuit was developed for two example applications and used for architectural system level performance analysis. Analysis of simulation results verified correct operation of the proposed hybrid dataflow system architecture and its dynamic load balancing circuit.