Reconfigurable computing with optical backplanes an economic argument for optical interconnects

A reconfigurable computing architecture which exploits the terabit bandwidth of a free-space optical backplane is proposed. The computing system consists of many printed circuit boards (PCBs), each containing a modest number of relatively inexpensive field programmable gate arrays (FPGAs). The PCBs are optically interconnected with an intelligent optical backplane using multiple smart pixel arrays on each PCB. Using current technologies this reconfigurable computing platform can sustain computing rates in the neighborhood of a TeraFlop per second for common scientific algorithms. The major costs of this platform are conservatively estimated at less than $1 Million. In contrast, according to [Patterson and Hennessy] a conventional RISC-based multiprocessor with 1 TeraFlop performance is not cost-effective using current technologies, but may be feasible in the year 2,000 at a cost approaching $100 million if electrical technology continues to mature. Our analysis indicates that a reconfigurable architecture will require one or two orders of magnitude less size (an optical backplane rack versus rows of electronic cabinets) and one or two orders of magnitude less cost than a conventional electronic RISC-based multi-processor architecture. Furthermore, our conclusions apply to similar optical networks with Terabit bandwidth capacities.