Output voltage integral control technique for compensating nonideal DC buses in voltage source inverters

Output harmonic minimization in standard pulse width modulation (PWM) pattern generators is based on the assumption that the input DC bus voltage is ripple-free. However, in a practical converter system, a nonideal DC bus deteriorates the quality of the inverter output voltage by introducing undesirable low-order harmonics that may be difficult to filter. The existing compensation techniques often use additional and complex circuitry to eliminate the effect of this ripple on the output voltage. This paper presents an online PWM pattern generator that inherently takes into account the DC bus ripple and generates gating signals required to produce high-quality sinusoidal output voltages. The technique is based on integrating the output voltage at a constant frequency on a pulse-by-pulse basis to ensure a sinusoidal volt-sec (V/s) distribution, irrespective of the input DC bus. The principles of operation are explained, and design equations are derived. The features of the proposed PWM pattern generator are illustrated. Comparison of the output voltage waveforms of those standard sinusoidal PWM (SPWM) techniques illustrate, in particular, the effectiveness of the ripple-rejection mechanism. Experimental results obtained on a 3-kVA laboratory prototype confirm the feasibility and features of the proposed pattern generator.