Efficient architecture for high-speed low-power SC ΣΔ modulators

A new solution to implement efficient switched-capacitor (SC) ΣΔ modulators is presented. The proposed modulator scheme employs an improved SC integrator topology in which voltage buffers are properly introduced. This allows the desired modulator sampling frequency to be obtained by significantly reducing the power consumption with respect to other existing schemes. Design examples of a ΣΔ modulator in a commercial 0.35-μm CMOS technology are reported. Simulation results show that the proposed solution allows a given modulator signal-to-noise and distortion ratio to be achieved by about halving the overall system power consumption.