A high-level synthesis approach to optimum design of self-checking circuits

We present an innovative solution to design of self checking systems implementing arithmetic algorithms. Rather than substituting self checking units in system synthesized independently of self checking requirements, we introduce self checking in high level synthesis as a requirement already for scheduling the DFG. Rules granting error detection allow optimum partitioning of the DFG; minimum latency, resource constrained scheduling is performed with the support of such partitioning so as to optimize the number of checkers as well as that of other resources.