Timing optimization by an improved redundancy addition and removal technique

Redundancy addition and removal (RAR) uses automatic test pattern generation (ATPG) techniques to identify logic optimization transforms. It has been applied successfully to combinational and sequential logic optimization and to layout driven logic synthesis for FPGAs. We present an improved RAR technique that allows to one to identify new types of optimization transforms and it is more efficient because it reduces the number of ATPG runs required. Also, we apply the RAR method to timing optimization. The experimental results show that this improved RAR technique produces significant timing optimization with very little area cost.