Architecture-aware data structure optimization for green IP lookup

Power consumption is becoming a limiting factor in next generation network routers. Recent observation shows that IP lookup engines dominate the power consumption of routers. Previous work on reducing power consumption of routers mainly focused on network-, system- and hardware-level optimizations. This paper represents the first attempt on the data structure optimization for power-efficient trie-based IP lookup engines. Both non-pipelined and pipelined static random access memory (SRAM) -based architectures are studied. Given the architecture, we formulate the problem by revisiting the time-space trade-off of multi-bit tries. A dynamic programming framework is then proposed to determine the optimal strides for building tree-bitmap tries so that the worst-case power consumption of the IP lookup engine is minimized. Experiments using real-life routing tables demonstrate that careful design of the data structure can reduce the power consumption dramatically. We hope our initial work can motivate the research community to expand their scope beyond the current efforts on either the hardware- or the system- and network- levels for power-efficient Internet infrastructure.