The FPGA implementation of the Log2(N, 0, p) switching fabric control algorithm

This paper presents a hardware implementation of a control algorithm for the log
2
(N, 0, p) switching fabric. This algorithm controls both connections and disconnections in the strict sense of a nonblocking switching fabric. The hardware implementation of this algorithm in Virtex5 circuits is described. The presented implementation has been optimized in order to minimize the time response of the controller. The controller is suitable to work in applications which require very fast (even immediate) decisions. Simulations were performed and the hardware implementation shows that the controller is able to determine a plane for a new connection in one clock cycle. After this clock cycle the controller is also ready for the next connection.