High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's

Recently, as multimedia large scale integrated devices (LSIs) have developed, there has been strongly increased demand for high-speed/high-bandwidth LSIs which integrate the DRAM core and logic elements (CPU etc.). However, the high-speed/high-bandwidth operation induces the large switching noise. This noise degrades the DRAM's operating margin, and especially its data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible design methodologies to maintain the reliability of high-speed/high-bandwidth system LSIs. We also show that good experimental results are obtained on the test device. Furthermore, we propose the most suitable V/sub DD//GND line scheme for on-chip DRAM system LSI.