Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs

The channel field and substrate current models developed for n-MOSFETs are applicable to p-MOSFETs. The impact ionization rate extracted for holes is found to be 8*10/sup 6/ exp (-3.7*10/sup 6//E), where E is the electric field. The lucky electron approach was used to model the gate current of surface-channel (SC) p-MOSFETs successfully. Device degradation in p-MOSFETs is due to trapped electrons in the oxide. p-MOSFET lifetime has good correlation with gate current in SC p-MOSFETs. The correlation is better than with substrate current. I/sub G/ can be larger in a buried-channel (BC) p-MOSFET than in a comparable SC n-MOSFET. This makes the SC MOSFET a much more reliable device. Device lifetime of a p-MOSFET under pulse stress can be predicted from DC stress data for inverterlike waveforms. For other waveforms, there is an extra degradation probably caused by the excess hot carriers generated during the gate turn-off transient.<
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