Design and optimization of a low-power and very-high-performance 0.25-/spl mu/m advanced PNP bipolar process

Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.