Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture

Concurrent communication architectures are essential in order to meet ever increasing demand for higher performance of modern-day System-on-Chip (SoC) applications. The behavior of such communication architectures is usually complex and difficult to model. This paper presents a formal modeling approach based on Stochastic Automata Network (SAN) for efficient performance evaluation of concurrent communication architectures. We use functional and synchronizing transitions of the SAN model to describe interaction among concurrent components of these architectures. We propose model for Network-on-Chip (NoC) architecture, and our modeling approach is able to provide evaluation of performance parameters viz. throughput and rate of accepted traffic for mesh, Torus and butterfly Fat Tree topologies. The proposed modeling approach is not only efficient and accurate but also requires lesser modeling efforts.