An advanced H.264/AVC CAVLC decoding architecture for low power implementation

This paper proposes a VLSI design of CAVLC decoder used in H.264/AVC. The previous CAVLC hardware decoders are inefficient architectures due to some reasons. Firstly, they contain unnecessary decoding cycle. Secondly, they have limitation for a decoding capability, that is made by flush unit and increase hardware cost. Then we propose the two methods to improve performance and implement a low power design. One is a method that eliminates unnecessary decoding cycle. The other is a method that uses the extended barrel shifter. The experimental result shows that the proposed architecture needs only 68 cycles in average for one macroblock decoding and this architecture improves the performance by about 45% comparing with the previous designs. It can be run under lower operating frequency than previous ones and it consumes lower power than previous ones. The synthesis result shows that the design achieves the maximum operating frequency at 125 MHz and the hardware cost is about 12.6K under a 0.18um CMOS process.