Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-on-Insulator

In this letter, hole mobility characteristics in Si gate-all-around nanowires on (110)-oriented silicon-on-insulator substrate have been studied, based on the advanced split C-V method. Fabricated nanowires have rectangular shape, and the height is fixed to 18 nm. High hole mobility in [110]-directed nanowires (widths ranging from 25 to 68 nm) were observed, illustrating 2.4 X enhancements over the universal (100) hole mobility in high N
_inv
region. Furthermore, effects of uniaxial stress in nanowires were investigated. It was found that [110]-directed nanowires were more sensitive to the applied stress in high N
_inv
region. Underlying physical mechanisms are also discussed.