A Semicustom VLSI System Design Course Supported by the General Electric Microelectronics Center

This paper presents an approach to VLSI system design and fabrication using gate arrays which has been implemented at the University of Virginia in conjunction with the General Electric Microelectronics Center (GE-MEC). Material initially developed by GE-MEC was modified and incorporated into a new graduate course to supplement that which already existed in the area of VLSI system design. A software tool set which includes functional and fault simulators for the TEGAS
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hardware description language, a testability analyzer, and packages for cell placement, channel routing, and system delay extraction was used for chip design. Chip fabrication of successful design projects is the responsibility of GE-MEC.