Test pattern generation for circuits with asynchronous signals based on scan

Several requirements must be satisfied to generate test patterns for scan designs. One important requirement is to prevent scan-in values from being destroyed. This is necessary to avoid unexpected asynchronous behavior as well as bus clash after applying the capture clock. This paper shows that constrained test pattern generation is very effective for this purpose. The constraints introduced in this paper change dynamically depending on values of the circuit. They are imposed on the pseudo-primary inputs or the pseudo-primary outputs so that the scan-in values are held after applying the capture clock. The patterns generated with the constraints are guaranteed to be valid even when a hazard occurs. Experimental results using actual devices show the efficiency of the proposed method.