Impact of Control-Gate and Floating-Gate Design on the Electron-Injection Spread of Decananometer nand Flash Memories

This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale nand Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.