Notice of Violation of IEEE Publication Principles: A novel Dynamic Voltage Scaling technique for low-power FPGA systems

Notice of Violation of IEEE Publication Principles

"A Novel Dynamic Voltage Scaling Technique for Low-Power FPGA Systems"
by V.L. Sreenivaas, D.Aravind Prasad, M. Kamalanathan, V.Vinith Kumar, S. Gayathri, M. Nandini
in the 2010 International Conference on Signal Processing and Communications (SPCOM), 2010, pp. 1 - 5

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control"
by Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
in the 2009 International SoC Design Conference (ISOCC), 2009, pp. 274 - 277


Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. This paper presents a low-power FPGA system with multiple supply voltage. The critical path of data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption. A novel DVS algorithm is presented, so that supply voltage to each logic block is made self-adaptive to the workload and data path, so as to minimize the power consumption without system performance degradation and been demonstrated using the FPGA system, a digitally adjustable DC-DC regulator and a power aware operating system. The simulations results show that up to 60% less energy is consumed with DVS than with a fixed supply voltage.