Effect of Anneal Time on the Enhanced Performance of a-Si:H TFTs for Future Display Technology

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as controlling devices for picture pixels in liquid crystal displays. In addition to flat panel display applications, a significant research effort focuses on the extension of this technology to circuitry on flexible substrates to build flexible sensor systems. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on Polyethylene naphthalate (PEN). Off-current is reduced by two orders of magnitude for 48-hours annealed TFT, and the sub-threshold slope become steeper with longer annealing. For positive gate-bias-stress, ΔV
_t
values are positive and exhibit a power-law time dependence (PLTD). The 48-hour annealed TFTs, however, display a turnaround phenomenon (TP) at longer stress times. For negative gate-bias-stress, TFTs annealed for ≥ 24 hours possess a smaller positive ΔV
_t
. They do not follow a PLTD and the TP is observed at longer stress times. The observed ΔV
_t
is explained in terms of the shift in the electron and hole transfer characteristics.