Abstract:
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circ...Show MoreMetadata
Abstract:
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The solution implements pattern matching logic for all the mandatory and optional patterns while maintaining the required line rate of 500 Mbps.
Published in: Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)
Date of Conference: 26-28 July 2010
Date Added to IEEE Xplore: 26 August 2010
ISBN Information:
Contents 