Integrated Circuit Architectures for High-Speed Time-Resolved Imaging

In this paper, two architectures for high-speed time-resolved imaging circuits in (Bi)CMOS technology are presented. The first architecture adopts the traditional for the most silicon imagers matrix configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a streak camera, coupled to an amplifier stage and an analog memory. The paper focuses on the design of a single vector-based time-resolved imager and presents recent results from a prototype fabricated in standard SiGe BiCMOS 0.35 μm technology. The circuit demonstrated a 6.7 ns Full Width at Half Maximum (FWHM) 532 nm laser pulse capture with very good accuracy and a 700 ps FWHM 650 nm laser diode pulse acquisition at 12 × 7.14 Gs/s.