Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and ${\rm I}_{\rm DDQ}$ Testing

This paper compares very-low-voltage (VLV) testing and quiescent power supply current (I
_DDQ
) testing for amorphous silicon thin-film transistor (a-Si TFT) NMOS digital circuits. As many as 140 circuits-under-test (CUT) of two different design styles are implemented in 8 μm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10 V) and very low voltage (7 V), followed by a 200-second voltage stress at 30 V. Seven unreliable CUT that escaped nominal voltage (NV) testing are successfully caught by VLV testing. The results indicate that VLV testing is more effective than I
_DDQ
testing to screen out unreliable a-Si TFT circuits. This study suggests that VLV testing is a non-destructive and economic alternative to burn-in for a-Si TFT circuits.