Minimization of threshold voltage variation to AVT=1.3mVµm in bulk high-k/metal gated devices by dopant-diffusion control using integrated FSP-FLA technology

We have successfully suppressed threshold voltage variations due to pattern effect problems and random dopant fluctuation (RDF) using an integrated FSP-FLA technology. The serious problem of the pattern effect in FLA can be solved by using a light-absorber carbon film process, together with FSP-FLA. We estimated the temperature range in our test chip was within 10°C, being the same level obtained with spike RTA. In addition, the diffusion-less feature of FLA reduces the RDF of NMOS down to the same level as with PMOS. By applying several optimized processes, including a high-k/metal gate stack, we achieved A
_VT
as 1.3mVμm for NMOS and 1.2mVμm for PMOS.