The design of low power 11.6mW high speed 1.8Gb/s stand-alone LVDS driver in 0.18-µm CMOS

This paper presents a design of power efficient and high speed transmitter implemented in CMOS 180 nm UMC technology, fully compatible with low voltage differential signaling (LVDS) standard specified by IEEE. The main stand-alone driver's functional blocks: LVDS core, common mode feedback (CMFB), control buffer and band-gap reference source are described in detail. Three architectures of LVDS transmitter cores: bridged-switched current source (BSCS), double current source (DCS) and open drain (OD) are compared and finally the BSCS architecture is selected due to project's requirements. The designed LVDS driver characterizes a very low level of static and dynamic power dissipation, P
_stat
= 7.5 mW and P
_dyn
= 11.6 mW respectively, at data speed transmission 1.8Gb/s with receiver's input capacitance C
_R
= 1 pF and P
_dyn
= 8.5 mW, data rates equals 400 Mb/s at C
_R
= 5 pF.