A universal model for calculating capacitive and resistive coupling on lightly and heavily doped CMOS processes

A new model for calculating capacitive and resistive coupling is developed in this work and its implementation in commonly encountered practical cases is presented. The model is based on the geometry of the coupling mechanism and is therefore, in general, scalable and technology independent, while pure 3D effects, like capacitive coupling, are fast and accurately computed. The proposed model is validated using measurements from a test chip in the UMC 0.18-μm CMOS lightly doped process, simulation data obtained by two commercial simulators and theoretical results. The accuracy of the model is shown to be within 2-10%.