A 90nm RFID tag's baseband processor with novel PIE decoder and uplink clock generator

A passive UHF RFID tag's baseband processor design with energy-aware structure is presented in this paper, based on EPC C1G2 protocol. For the consideration of limited availability of power and low-voltage supply, ripple-binary mixed counter and compensated addition are proposed for the PIE decoder. And in the clock generator for tag-to-reader uplink, Galoi linear feedback shift register (LFSR) is utilized to satisfy critical timing requirement. Additionally, double-edge-triggered (DET) flip flop in these two modules helps to improve clock efficiency and reduce the impact of frequency variation at low voltage power supply. Therefore the robustness of the processor is ensured. The whole tag was fabricated in standard 90nm CMOS technology, and in measurement the baseband processor can consume less than 80nW at 0.33V supply.