A Silicon Interposer With an Integrated ${\rm SrTiO}_{3}$ Thin Film Decoupling Capacitor and Through-Silicon Vias

A silicon interposer with an integrated with SrTiO
₃
(STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm
²
was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm
²
area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.