A low glitch 14-bit 100 MHz D/A converter

A low glitch 14-bit 100 MHz BiCMOS current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSBs) into fifteen equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. An innovative bidirectional trim network minimizes the amount of laser trim required to achieve 14-bit accuracy, resulting in less post-trim degradation of integral and differential nonlinearity (INL and DNL) over temperature and lifetime of the chip. High /spl beta/ n-p-n devices were used in the precision current cells and switches to reduce post-trim degradation of DAC linearity over temperature. The converter has been fabricated in a 4 GHz/1.4 /spl mu/m BiCMOS technology and exhibits a measured glitch energy of 0.5 pV-s (singlet). Settling time to within /spl plusmn/0.024% of the final value is 20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at a clock rate of 10 MHz and an output frequency of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09 mm /spl times/4.09 mm which includes bond pads and electrostatic discharge (ESD) protection devices.