A 10 bit, 2Ms/s, 15 mW BiCMOS cyclic RSD A/D converter

A 10 bit, 2 megasamples per second (Ms/s) BiCMOS cyclic analog to digital converter (ADC) is presented. The ADC is optimized for low power operation and employs digital error correction based on the redundant signed digit (RSD) principle to correct for gain and offset errors.