A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl mu/A//spl mu/m (1.0 V) are achieved. Target L/sub g//sup min/ (minimum gate length)=0.15-0.16 /spl mu/m. Drive currents are comparable to a recently reported 0.08 /spl mu/m CMOS process. Low nMOS R/sub SD/<220 /spl Omega/-/spl mu/m and pMOS R/sub SD/<500 /spl Omega/-/spl mu/m are achieved. Improvements to 1.5 V CMOS include CoSi/sub 2/ cladding, pocket implant for n- and pMOS, increased HDD and S/D dose with increased anneal, and low temperature backend processing <700/spl deg/C. Scaling of the 1.5 V CMOS to 1.0 V CMOS is achieved by (a) reduction of V/sub T/ implant dose or (b) use of shallow channel counterdoping (CD) if the V/sub T/ dose cannot be reduced further. With reduced V/sub T/ dose, nominal V/sub T//sup sat/ is reduced from 0.25 V (1.5 V CMOS) to 0.10 V (1.0 V CMOS) with small short-channel effect (SCE) for both designs. With CD and same pocket process from 1.5 V CMOS, low V/sub T/ devices are achieved with lower and constant V/sub t//sup sat/=0.06 V from L/sub gate/=0.25-0.25 /spl mu/m and with low SCE. Inverter chain delay of 37 psec for the 1.0 V, 36 A, 0.18 /spl mu/m CMOS is reduced 40% compared to a prior 1.0 V, 48 A, 0.25 /spl mu/m process.