A forward body bias generator for digital CMOS circuits with supply voltage scaling

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm
²
. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm
²
occupies a silicon area of 0.03mm
²
only. The generator completes a 500mV FBB voltage step within 4μs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177μA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C.