High performance CMOS current comparator design

The paper describes some design aspects in the implementation of CMOS current comparators. More specifically, techniques for offset and charge-injection compensations are discussed in detail, and some basic topologies for compensated current comparators are presented and compared by SPICE simulations. Moreover, a novel compensated fully differential current comparator is proposed which achieves a very high performance. It provides a sensitivity as low as 20 nA and a switching time better than 30 ns with a 0.5 /spl mu/A input step current while dissipating 45 /spl mu/W.